1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device having a voltage detection circuit capable of detecting a high-voltage test command signal supplied when a test is conducted.
2. Description of the Background Art
A test for a semiconductor memory device having no exclusive test terminal, especially a test after packaging, is carried out by applying a test command voltage higher than the range of an input voltage applied to a specified input/output terminal in a normal operation so as to cause transition of the semiconductor memory device to a desired test state. In this case, the test command voltage applied is higher than the input voltage range for the normal operation in order to prevent an erroneous transition to the test mode of the semiconductor memory device in the normal operation.
As shown in FIG. 5, a conventional semiconductor memory device 200 includes a test circuit 210 and a test target circuit 250. Test circuit 210 includes a delay circuit 220, a voltage detection circuit 230, and a test mode transition circuit 240. Test target circuit 250 includes an input/output interface circuit 260.
Delay circuit 220 generates signals SVDEND and SVDENF according to an activation signal SVDEN and outputs the resultant signals to voltage detection circuit 230. Voltage detection circuit 230 is activated according to signals SVDEND and SVDENF from delay circuit 220 to detect a test command signal EXTSH supplied from an input/output terminal in a manner described later, and output a result of the detection to test mode transition circuit 240.
Test mode transition circuit 240 provides, when a signal DET indicating detection of test command signal EXTSH is supplied from voltage detection circuit 230, a test mode transition signal TME to test target circuit 250 via input/output interface circuit 260 to cause transition of test target circuit 250 to a test mode.
Referring to FIG. 6, conventional voltage detection circuit 230 includes N channel MOS transistors 301-304, 310-315 and 317, and P channel MOS transistors 307-309 and 316. N channel MOS transistors 301-304 are connected in series between an input node N10 and a ground node 305. N channel MOS transistors 301-304 constitute a voltage division circuit 320 that is activated according to turn-on of N channel MOS transistor 304. N channel MOS transistors 301-304 derive from a voltage of test command signal EXISH a fraction thereof and output the voltage fraction to a node N11.
P channel MOS transistors 308 and 309 and N channel MOS transistors 310-312 constitute a comparison circuit 330 of the differential amplification type, amplifying a result of comparison between a voltage on a node N12 and a voltage on node N11 to output the amplified result to a node N13. Comparison circuit 330 is disposed between ground node 305 and a power supply node 306 applied with an external supply voltage.
N channel MOS transistors 313-315 are connected in series between ground node 305 and power supply node 306 to constitute a voltage division circuit 340 that is activated by turn-on of N channel MOS transistor 315. Voltage division circuit 340 derives from the external supply voltage applied to supply node 306 a fraction thereof and outputs the voltage fraction to node N12.
P channel MOS transistor 316 and N channel MOS transistor 317 constitute an inverter 350, converting an analog signal on node N13 that is the output of comparison circuit 330 into a logic signal according to its magnitude.
P channel MOS transistor 307 and N channel MOS transistor 312 are turned on/off according to signal SVDEND to activate or inactivate comparison circuit 330. N channel MOS transistors 304 and 315 are turned on/off according to signal SVDENF to activate or inactivate voltage division circuits 320 and 340 respectively.
Voltage detection circuit 230 has its input node N10 receiving test command signal EXTSH when transition of semiconductor memory device 200 to a test mode is to be caused. Test command signal EXTSH is formed of a voltage higher than an input voltage range in a normal operation.
Voltage division circuit 320 uses N channel MOS transistors 301-303 to derive from the voltage forming the test command signal a fraction thereof and output the voltage fraction to node N11. Voltage division circuit 340 uses N channel MOS transistors 313 and 314 to derive from the external supply voltage a fraction thereof and output the voltage fraction to node N12. The voltage resulting from the division on node N12 is then compared with the voltage resulting from the division on node N11 by N channel MOS transistors 310 and 311. Aresult of the comparison is amplified by P channel MOS transistors 308 and 309 to be supplied to node N13.
If the voltage on node N11 is higher than the voltage on node N12, comparison circuit 330 provides a voltage V1, which is lower than a voltage on a node N14 connecting P channel MOS transistor 309 and N channel MOS transistor 311, to node N13. If the voltage on node N11 is lower than the voltage on node N12, comparison circuit 330 provides a voltage V2 higher than the voltage on node N14.
Accordingly, if a voltage to cause switch between on and off of P channel MOS transistor 316 and N channel MOS transistor 317 is set between voltage V1 and voltage V2, inverter 350 outputs a logic signal SVIHDET of an H (logical high) level when voltage V1 on node N13 is applied and outputs logic signal SVIHDET of an L (logical low) level when voltage V2 on node N13 is applied. In other words, if a voltage resulting from division of a voltage forming test command signal EXTSH is higher than a voltage resulting from division of an external supply voltage, inverter 350 outputs logic signal SVIHDET of H level. If the voltage resulting from division of the voltage forming test command signal EXTSH is lower than the voltage resulting from division of the external supply voltage, inverter 350 outputs logic signal SVIHDET of L level.
Then, the output of logic signal SVIHDET of H level from voltage detection circuit 230 means that test command signal EXTSH is detected, while the output of logic signal SVIHDET of L level from voltage detection circuit 230 means that test command signal EXTSH is not detected. Logic signal SVIHDET of H level constitutes signal DET indicating detection of test command signal EXTSH.
Test mode transition circuit 240 provides test mode signal TME to test target circuit 250 when test mode transition circuit 240 receives logic signal SVIHDET (signal DET) of H level from voltage detection circuit 230. Receiving test mode signal TME via input/output interface circuit 260, test target circuit 250 makes transition to a test mode.
When voltage detection circuit 230 is inactive, N channel MOS transistors 304 and 315 are turned off. A potential on node N12 is thus set at the external supply voltage applied from power supply node 306. On the other hand, a potential on node N11, which is not fixed at the external supply voltage nor a ground potential, is equal to a potential on node N10 receiving test command signal EXTSH. In this state, suppose that signal SVDENF of H level is applied to turn on N channel MOS transistors 304 and 315, causing transition of voltage division circuits 320 and 340 from an inactive state to an active state, and a voltage lower than the high voltage of the test command signal and higher than the external supply voltage is applied to node N10. In this case, the potential on node N12 is higher than the potential on node N11 and any malfunction could occur in the period in which the potentials on nodes N11 and N12 are corrected to proper voltages that are obtained by voltage division.
In order to solve this problem, as shown in FIG. 7, delay circuit 220 having a delay unit 221, inverters 222, 223 and 225 and an NOR gate 224 is provided. Signals SVDEND and SVDENF following the timing chart shown in FIG. 8 are generated from activation signal SVDEN, signal SVDEND is supplied to P channel MOS transistors 307 and N channel MOS transistor 312 that activate comparison circuit 330, and signal SVDENF is supplied to N channel MOS transistors 304 and 315 that activate voltage division circuits 320 and 340. Specifically, as shown in FIG. 8, signal SVDEND is delayed with respect to signal SVDENF by a predetermined time T, voltage division circuits 320 and 340 are activated, and comparison circuit 330 is thereafter activated after respective potentials on node N11 and node N12 return to correct voltages respectively that result from voltage division. In this way, the problem above of malfunction can be solved.
The method described above is used to detect test command signal EXTSH by voltage detection circuit 230, cause transition of test target circuit 250 to a test mode, thereafter input a specified pattern from input/output terminals for address signals via input/output interface circuit 260 and accordingly conduct a test for test target circuit 250.
However, there is a problem that test command signal EXTSH cannot be detected in a stable manner. This is because voltage division circuits 320 and 340 of voltage detection circuit 230 are constructed of N channel MOS transistors operating under different conditions, and variation in manufacturing conditions for the N channel MOS transistors could change a detectable voltage value.
Specifically, N channel MOS transistors 301 and 302 that constitute voltage division circuit 320 together with N channel MOS transistor 303 operate in resistance mode (meaning diode connection, which is applied hereinafter), and N channel MOS transistor 303 operates in threshold mode. N channel MOS transistor 313, which is one of N channel MOS transistors 313 and 314 constituting voltage division circuit 340, operates in resistance mode while the other N channel MOS transistor 314 operates in threshold mode. Accordingly, a voltage resulting from division by voltage division circuits 320 and 340 each is not equal to the voltage determined by dividing an original voltage by the number of N channel MOS transistors. In order to keep a detected voltage at a constant value, both of the threshold and channel resistance of the N channel MOS transistors constituting voltage division circuits 320 and 340 should be controlled. Then, change of manufacturing conditions for the N channel MOS transistors would readily cause changes in threshold voltage and channel resistance, making it impossible to maintain a detected voltage at a constant value.
Another problem is increase in size of test circuit 210, since a large area is occupied by delay circuit 220 which is arranged on semiconductor memory device 200 for preventing a malfunction in transition from the inactive state to the active state as discussed above.